Map pci interrupts to ioapic on ia64

kvm/ia64's pci interrupts map to the 16-47 range, but current Qemu doesn't
support this.  Here we implment a IRQ map function to solve this issue to
enable pci interrupts.

Signed-off-by: Anthony Xu <anthony.xu@intel.com>
Signed-off-by: Xiantao Zhang <xiantao.zhang@intel.com>
Signed-off-by: Avi Kivity <avi@qumranet.com>

1 files changed, 29 insertions, 0 deletions

diff --git a/hw/ipf.c b/hw/ipf.c
index c1a7bee43..cdb766b05 100644
--- a/hw/ipf.c
+++ b/hw/ipf.c
@@ -683,3 +683,32 @@ QEMUMachine ipf_machine = {
     ipf_init_pci,
     VGA_RAM_SIZE + GFW_SIZE,
 };
+
+#define IOAPIC_NUM_PINS 48
+
+static int ioapic_irq_count[IOAPIC_NUM_PINS];
+
+static int ioapic_map_irq(int devfn, int irq_num)
+{
+    int irq, dev;
+    dev = devfn >> 3;
+    irq = ((((dev << 2) + (dev >> 3) + irq_num) & 31) + 16);
+    return irq;
+}
+
+void ioapic_set_irq(void *opaque, int irq_num, int level)
+{
+    int vector;
+
+    PCIDevice *pci_dev = (PCIDevice *)opaque;
+    vector = ioapic_map_irq(pci_dev->devfn, irq_num);
+
+    if (level)
+        ioapic_irq_count[vector] += 1;
+    else
+        ioapic_irq_count[vector] -= 1;
+
+    if (kvm_enabled())
+	if (kvm_set_irq(vector, ioapic_irq_count[vector] == 0))
+	    return;
+}