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author | 2007-04-17 16:28:29 +0000 | |
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committer | 2007-04-17 16:28:29 +0000 | |
commit | 18c6e2ff5adc016031566f409382417f6fde626d (patch) | |
tree | 675a465350b75b06adcb824b2f10ec350ed6dc54 /hw/mc146818rtc.c | |
parent | Choose number of TLBs at runtime, by Herve Poussineau. (diff) | |
download | qemu-kvm-18c6e2ff5adc016031566f409382417f6fde626d.tar.gz qemu-kvm-18c6e2ff5adc016031566f409382417f6fde626d.tar.bz2 qemu-kvm-18c6e2ff5adc016031566f409382417f6fde626d.zip |
Fix mmapped register alignment and endianness handling.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2694 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'hw/mc146818rtc.c')
-rw-r--r-- | hw/mc146818rtc.c | 35 |
1 files changed, 25 insertions, 10 deletions
diff --git a/hw/mc146818rtc.c b/hw/mc146818rtc.c index af7665495..e30791f8a 100644 --- a/hw/mc146818rtc.c +++ b/hw/mc146818rtc.c @@ -56,6 +56,7 @@ struct RTCState { struct tm current_tm; qemu_irq irq; target_phys_addr_t base; + int it_shift; /* periodic timer */ QEMUTimer *periodic_timer; int64_t next_periodic_time; @@ -492,7 +493,7 @@ uint32_t cmos_mm_readb (void *opaque, target_phys_addr_t addr) { RTCState *s = opaque; - return cmos_ioport_read(s, addr - s->base) & 0xFF; + return cmos_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFF; } void cmos_mm_writeb (void *opaque, @@ -500,37 +501,51 @@ void cmos_mm_writeb (void *opaque, { RTCState *s = opaque; - cmos_ioport_write(s, addr - s->base, value & 0xFF); + cmos_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFF); } uint32_t cmos_mm_readw (void *opaque, target_phys_addr_t addr) { RTCState *s = opaque; + uint32_t val; - return cmos_ioport_read(s, addr - s->base) & 0xFFFF; + val = cmos_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFFFF; +#ifdef TARGET_WORDS_BIGENDIAN + val = bswap16(val); +#endif + return val; } void cmos_mm_writew (void *opaque, target_phys_addr_t addr, uint32_t value) { RTCState *s = opaque; - - cmos_ioport_write(s, addr - s->base, value & 0xFFFF); +#ifdef TARGET_WORDS_BIGENDIAN + value = bswap16(value); +#endif + cmos_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFFFF); } uint32_t cmos_mm_readl (void *opaque, target_phys_addr_t addr) { RTCState *s = opaque; + uint32_t val; - return cmos_ioport_read(s, addr - s->base); + val = cmos_ioport_read(s, (addr - s->base) >> s->it_shift); +#ifdef TARGET_WORDS_BIGENDIAN + val = bswap32(val); +#endif + return val; } void cmos_mm_writel (void *opaque, target_phys_addr_t addr, uint32_t value) { RTCState *s = opaque; - - cmos_ioport_write(s, addr - s->base, value); +#ifdef TARGET_WORDS_BIGENDIAN + value = bswap32(value); +#endif + cmos_ioport_write(s, (addr - s->base) >> s->it_shift, value); } static CPUReadMemoryFunc *rtc_mm_read[] = { @@ -545,7 +560,7 @@ static CPUWriteMemoryFunc *rtc_mm_write[] = { &cmos_mm_writel, }; -RTCState *rtc_mm_init(target_phys_addr_t base, qemu_irq irq) +RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq) { RTCState *s; int io_memory; @@ -574,7 +589,7 @@ RTCState *rtc_mm_init(target_phys_addr_t base, qemu_irq irq) qemu_mod_timer(s->second_timer2, s->next_second_time); io_memory = cpu_register_io_memory(0, rtc_mm_read, rtc_mm_write, s); - cpu_register_physical_memory(base, 2, io_memory); + cpu_register_physical_memory(base, 2 << it_shift, io_memory); register_savevm("mc146818rtc", base, 1, rtc_save, rtc_load, s); return s; |