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authoraurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162>2008-12-18 22:43:40 +0000
committeraurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162>2008-12-18 22:43:40 +0000
commit475dc65f6d33d8f457d5731c38618b0b3d4e127c (patch)
tree6ecdf4863bec8c4d42d8f259239afb6d70a90829 /hw
parentPCI: Mask writes to RO bits in the status reg of PCI config space (diff)
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PCI: Mask writes to RO bits in the command reg of PCI config space
The Command register in the PCI config space has some read-only bits. Any writes to those bits should be masked out. Signed-off-by: Amit Shah <amit.shah@redhat.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6092 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'hw')
-rw-r--r--hw/pci.c3
-rw-r--r--hw/pci.h5
2 files changed, 8 insertions, 0 deletions
diff --git a/hw/pci.c b/hw/pci.c
index b95c79440..8252d21b9 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -417,6 +417,9 @@ void pci_default_write_config(PCIDevice *d,
if (can_write) {
/* Mask out writes to reserved bits in registers */
switch (addr) {
+ case 0x05:
+ val &= ~PCI_COMMAND_RESERVED_MASK_HI;
+ break;
case 0x06:
val &= ~PCI_STATUS_RESERVED_MASK_LO;
break;
diff --git a/hw/pci.h b/hw/pci.h
index 95905db1e..3b1caf5ca 100644
--- a/hw/pci.h
+++ b/hw/pci.h
@@ -69,6 +69,11 @@ typedef struct PCIIORegion {
#define PCI_STATUS_RESERVED_MASK_HI (PCI_STATUS_DEVSEL >> 8)
+/* Bits in the PCI Command Register (PCI 2.3 spec) */
+#define PCI_COMMAND_RESERVED 0xf800
+
+#define PCI_COMMAND_RESERVED_MASK_HI (PCI_COMMAND_RESERVED >> 8)
+
struct PCIDevice {
/* PCI config space */
uint8_t config[256];