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| author |   aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162> | 2009-03-29 00:13:56 +0000 |
|---|---|---|
| committer | aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162> | 2009-03-29 00:13:56 +0000 |
| commit | a15167446259805dcd7e639261b2413e07654040 (patch) | |
| tree | 4028cee3c736ed57e68c3b7914a9423a23d4aee1 /target-alpha | |
| parent | target-alpha: Fix bug: do not mask address LSBs for ldwu. (diff) | |
| download | qemu-kvm-a15167446259805dcd7e639261b2413e07654040.tar.gz qemu-kvm-a15167446259805dcd7e639261b2413e07654040.tar.bz2 qemu-kvm-a15167446259805dcd7e639261b2413e07654040.zip | |
target-alpha: fix bug: integer conditional branch offset is 21 bits wide.
Signed-off-by: Tristan Gingold <gingold@adacore.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6924 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-alpha')
| -rw-r--r-- | target-alpha/translate.c | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/target-alpha/translate.c b/target-alpha/translate.c index b827ba2b9..7b28abcd3 100644 --- a/target-alpha/translate.c +++ b/target-alpha/translate.c @@ -290,7 +290,7 @@ static always_inline void gen_store_mem (DisasContext *ctx, static always_inline void gen_bcond (DisasContext *ctx, TCGCond cond, - int ra, int32_t disp16, int mask) + int ra, int32_t disp, int mask) { int l1, l2; @@ -313,7 +313,7 @@ static always_inline void gen_bcond (DisasContext *ctx, tcg_gen_movi_i64(cpu_pc, ctx->pc); tcg_gen_br(l2); gen_set_label(l1); - tcg_gen_movi_i64(cpu_pc, ctx->pc + (int64_t)(disp16 << 2)); + tcg_gen_movi_i64(cpu_pc, ctx->pc + (int64_t)(disp << 2)); gen_set_label(l2); } @@ -2285,42 +2285,42 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) break; case 0x38: /* BLBC */ - gen_bcond(ctx, TCG_COND_EQ, ra, disp16, 1); + gen_bcond(ctx, TCG_COND_EQ, ra, disp21, 1); ret = 1; break; case 0x39: /* BEQ */ - gen_bcond(ctx, TCG_COND_EQ, ra, disp16, 0); + gen_bcond(ctx, TCG_COND_EQ, ra, disp21, 0); ret = 1; break; case 0x3A: /* BLT */ - gen_bcond(ctx, TCG_COND_LT, ra, disp16, 0); + gen_bcond(ctx, TCG_COND_LT, ra, disp21, 0); ret = 1; break; case 0x3B: /* BLE */ - gen_bcond(ctx, TCG_COND_LE, ra, disp16, 0); + gen_bcond(ctx, TCG_COND_LE, ra, disp21, 0); ret = 1; break; case 0x3C: /* BLBS */ - gen_bcond(ctx, TCG_COND_NE, ra, disp16, 1); + gen_bcond(ctx, TCG_COND_NE, ra, disp21, 1); ret = 1; break; case 0x3D: /* BNE */ - gen_bcond(ctx, TCG_COND_NE, ra, disp16, 0); + gen_bcond(ctx, TCG_COND_NE, ra, disp21, 0); ret = 1; break; case 0x3E: /* BGE */ - gen_bcond(ctx, TCG_COND_GE, ra, disp16, 0); + gen_bcond(ctx, TCG_COND_GE, ra, disp21, 0); ret = 1; break; case 0x3F: /* BGT */ - gen_bcond(ctx, TCG_COND_GT, ra, disp16, 0); + gen_bcond(ctx, TCG_COND_GT, ra, disp21, 0); ret = 1; break; invalid_opc: |