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| author |   Andre Przywara <andre.przywara@amd.com> | 2009-09-19 00:30:49 +0200 |
|---|---|---|
| committer |   Aurelien Jarno <aurelien@aurel32.net> | 2009-10-04 14:46:34 +0200 |
| commit | 1b050077d2d72b15c73257c13e2e46932786f7e2 (patch) | |
| tree | dc42c285ca15dc1901ef7f6ae268d583521300d5 /target-i386/cpu.h | |
| parent | target-i386: add SSE4a instruction support (diff) | |
| download | qemu-kvm-1b050077d2d72b15c73257c13e2e46932786f7e2.tar.gz qemu-kvm-1b050077d2d72b15c73257c13e2e46932786f7e2.tar.bz2 qemu-kvm-1b050077d2d72b15c73257c13e2e46932786f7e2.zip | |
target-i386: add RDTSCP support
RDTSCP reads the time stamp counter and atomically also the content
of a 32-bit MSR, which can be freely set by the OS. This allows CPU
local data to be queried by userspace.
Linux uses this to allow a fast implementation of the getcpu()
syscall, which uses the vsyscall page to avoid a context switch.
AMD CPUs since K8RevF and Intel CPUs since Nehalem support this
instruction.
RDTSCP is guarded by the RDTSCP CPUID bit (Fn8000_0001:EDX[27]).
Signed-off-by: Andre Przywara <andre.przywara@amd.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-i386/cpu.h')
| -rw-r--r-- | target-i386/cpu.h | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/target-i386/cpu.h b/target-i386/cpu.h index b9a6392cf..f318942ee 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -322,6 +322,7 @@ #define MSR_FSBASE 0xc0000100 #define MSR_GSBASE 0xc0000101 #define MSR_KERNELGSBASE 0xc0000102 +#define MSR_TSC_AUX 0xc0000103 #define MSR_VM_HSAVE_PA 0xc0010117 @@ -694,6 +695,8 @@ typedef struct CPUX86State { uint64 mcg_status; uint64 mcg_ctl; uint64 *mce_banks; + + uint64_t tsc_aux; } CPUX86State; CPUX86State *cpu_x86_init(const char *cpu_model); @@ -854,7 +857,7 @@ uint64_t cpu_get_tsc(CPUX86State *env); #define cpu_signal_handler cpu_x86_signal_handler #define cpu_list x86_cpu_list -#define CPU_SAVE_VERSION 10 +#define CPU_SAVE_VERSION 11 /* MMU modes definitions */ #define MMU_MODE0_SUFFIX _kernel |