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| author |   Andre Przywara <andre.przywara@amd.com> | 2009-09-19 00:30:49 +0200 |
|---|---|---|
| committer |   Aurelien Jarno <aurelien@aurel32.net> | 2009-10-04 14:46:34 +0200 |
| commit | 1b050077d2d72b15c73257c13e2e46932786f7e2 (patch) | |
| tree | dc42c285ca15dc1901ef7f6ae268d583521300d5 /target-i386/machine.c | |
| parent | target-i386: add SSE4a instruction support (diff) | |
| download | qemu-kvm-1b050077d2d72b15c73257c13e2e46932786f7e2.tar.gz qemu-kvm-1b050077d2d72b15c73257c13e2e46932786f7e2.tar.bz2 qemu-kvm-1b050077d2d72b15c73257c13e2e46932786f7e2.zip | |
target-i386: add RDTSCP support
RDTSCP reads the time stamp counter and atomically also the content
of a 32-bit MSR, which can be freely set by the OS. This allows CPU
local data to be queried by userspace.
Linux uses this to allow a fast implementation of the getcpu()
syscall, which uses the vsyscall page to avoid a context switch.
AMD CPUs since K8RevF and Intel CPUs since Nehalem support this
instruction.
RDTSCP is guarded by the RDTSCP CPUID bit (Fn8000_0001:EDX[27]).
Signed-off-by: Andre Przywara <andre.przywara@amd.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-i386/machine.c')
| -rw-r--r-- | target-i386/machine.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/target-i386/machine.c b/target-i386/machine.c index ab3132902..e5a060fcc 100644 --- a/target-i386/machine.c +++ b/target-i386/machine.c @@ -171,6 +171,7 @@ void cpu_save(QEMUFile *f, void *opaque) qemu_put_be64s(f, &env->mce_banks[4*i + 3]); } } + qemu_put_be64s(f, &env->tsc_aux); } #ifdef USE_X86LDOUBLE @@ -377,6 +378,9 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id) } } + if (version_id >= 11) { + qemu_get_be64s(f, &env->tsc_aux); + } /* XXX: ensure compatiblity for halted bit ? */ /* XXX: compute redundant hflags bits */ env->hflags = hflags; |