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| author |   blueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-11-09 19:50:37 +0000 |
|---|---|---|
| committer | blueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-11-09 19:50:37 +0000 |
| commit | 81b5b816e23450c4659411f77d9c7b54681e07dc (patch) | |
| tree | 8ac0431eff77a9f06f1ec620397f832fe3ae32a1 /target-sparc | |
| parent | target-ppc: fix TCG argument (diff) | |
| download | qemu-kvm-81b5b816e23450c4659411f77d9c7b54681e07dc.tar.gz qemu-kvm-81b5b816e23450c4659411f77d9c7b54681e07dc.tar.bz2 qemu-kvm-81b5b816e23450c4659411f77d9c7b54681e07dc.zip | |
Use andc, orc, nor and nand
Also fix which argument gets negated in fandnot[12] and fornot[12]
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5662 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-sparc')
| -rw-r--r-- | target-sparc/translate.c | 88 |
1 files changed, 36 insertions, 52 deletions
diff --git a/target-sparc/translate.c b/target-sparc/translate.c index 63c338b20..40faa285e 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -3079,14 +3079,12 @@ static void disas_sparc_insn(DisasContext * dc) tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_src2); break; case 0x5: - tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1); - tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_tmp0); + tcg_gen_andc_tl(cpu_dst, cpu_src1, cpu_src2); if (xop & 0x10) gen_op_logic_cc(cpu_dst); break; case 0x6: - tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1); - tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_tmp0); + tcg_gen_orc_tl(cpu_dst, cpu_src1, cpu_src2); if (xop & 0x10) gen_op_logic_cc(cpu_dst); break; @@ -3907,31 +3905,26 @@ static void disas_sparc_insn(DisasContext * dc) break; case 0x062: /* VIS I fnor */ CHECK_FPU_FEATURE(dc, VIS1); - tcg_gen_or_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1)], - cpu_fpr[DFPREG(rs2)]); - tcg_gen_xori_i32(cpu_fpr[DFPREG(rd)], cpu_tmp32, -1); - tcg_gen_or_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1) + 1], - cpu_fpr[DFPREG(rs2) + 1]); - tcg_gen_xori_i32(cpu_fpr[DFPREG(rd) + 1], cpu_tmp32, -1); + tcg_gen_nor_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1)], + cpu_fpr[DFPREG(rs2)]); + tcg_gen_nor_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1) + 1], + cpu_fpr[DFPREG(rs2) + 1]); break; case 0x063: /* VIS I fnors */ CHECK_FPU_FEATURE(dc, VIS1); - tcg_gen_or_i32(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]); - tcg_gen_xori_i32(cpu_fpr[rd], cpu_tmp32, -1); + tcg_gen_nor_i32(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]); break; case 0x064: /* VIS I fandnot2 */ CHECK_FPU_FEATURE(dc, VIS1); - tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1)], -1); - tcg_gen_and_i32(cpu_fpr[DFPREG(rd)], cpu_tmp32, - cpu_fpr[DFPREG(rs2)]); - tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1) + 1], -1); - tcg_gen_and_i32(cpu_fpr[DFPREG(rd) + 1], cpu_tmp32, - cpu_fpr[DFPREG(rs2) + 1]); + tcg_gen_andc_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)], + cpu_fpr[DFPREG(rs2)]); + tcg_gen_andc_i32(cpu_fpr[DFPREG(rd) + 1], + cpu_fpr[DFPREG(rs1) + 1], + cpu_fpr[DFPREG(rs2) + 1]); break; case 0x065: /* VIS I fandnot2s */ CHECK_FPU_FEATURE(dc, VIS1); - tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[rs1], -1); - tcg_gen_and_i32(cpu_fpr[rd], cpu_tmp32, cpu_fpr[rs2]); + tcg_gen_andc_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]); break; case 0x066: /* VIS I fnot2 */ CHECK_FPU_FEATURE(dc, VIS1); @@ -3946,17 +3939,15 @@ static void disas_sparc_insn(DisasContext * dc) break; case 0x068: /* VIS I fandnot1 */ CHECK_FPU_FEATURE(dc, VIS1); - tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs2)], -1); - tcg_gen_and_i32(cpu_fpr[DFPREG(rd)], cpu_tmp32, - cpu_fpr[DFPREG(rs1)]); - tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs2)], -1); - tcg_gen_and_i32(cpu_fpr[DFPREG(rd) + 1], cpu_tmp32, - cpu_fpr[DFPREG(rs1) + 1]); + tcg_gen_andc_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs2)], + cpu_fpr[DFPREG(rs1)]); + tcg_gen_andc_i32(cpu_fpr[DFPREG(rd) + 1], + cpu_fpr[DFPREG(rs2) + 1], + cpu_fpr[DFPREG(rs1) + 1]); break; case 0x069: /* VIS I fandnot1s */ CHECK_FPU_FEATURE(dc, VIS1); - tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[rs2], -1); - tcg_gen_and_i32(cpu_fpr[rd], cpu_tmp32, cpu_fpr[rs1]); + tcg_gen_andc_i32(cpu_fpr[rd], cpu_fpr[rs2], cpu_fpr[rs1]); break; case 0x06a: /* VIS I fnot1 */ CHECK_FPU_FEATURE(dc, VIS1); @@ -3983,17 +3974,14 @@ static void disas_sparc_insn(DisasContext * dc) break; case 0x06e: /* VIS I fnand */ CHECK_FPU_FEATURE(dc, VIS1); - tcg_gen_and_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1)], - cpu_fpr[DFPREG(rs2)]); - tcg_gen_xori_i32(cpu_fpr[DFPREG(rd)], cpu_tmp32, -1); - tcg_gen_and_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1) + 1], - cpu_fpr[DFPREG(rs2) + 1]); - tcg_gen_xori_i32(cpu_fpr[DFPREG(rd) + 1], cpu_tmp32, -1); + tcg_gen_nand_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1)], + cpu_fpr[DFPREG(rs2)]); + tcg_gen_nand_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1) + 1], + cpu_fpr[DFPREG(rs2) + 1]); break; case 0x06f: /* VIS I fnands */ CHECK_FPU_FEATURE(dc, VIS1); - tcg_gen_and_i32(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]); - tcg_gen_xori_i32(cpu_fpr[rd], cpu_tmp32, -1); + tcg_gen_nand_i32(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]); break; case 0x070: /* VIS I fand */ CHECK_FPU_FEATURE(dc, VIS1); @@ -4033,17 +4021,15 @@ static void disas_sparc_insn(DisasContext * dc) break; case 0x076: /* VIS I fornot2 */ CHECK_FPU_FEATURE(dc, VIS1); - tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1)], -1); - tcg_gen_or_i32(cpu_fpr[DFPREG(rd)], cpu_tmp32, - cpu_fpr[DFPREG(rs2)]); - tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1) + 1], -1); - tcg_gen_or_i32(cpu_fpr[DFPREG(rd) + 1], cpu_tmp32, - cpu_fpr[DFPREG(rs2) + 1]); + tcg_gen_orc_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)], + cpu_fpr[DFPREG(rs2)]); + tcg_gen_orc_i32(cpu_fpr[DFPREG(rd) + 1], + cpu_fpr[DFPREG(rs1) + 1], + cpu_fpr[DFPREG(rs2) + 1]); break; case 0x077: /* VIS I fornot2s */ CHECK_FPU_FEATURE(dc, VIS1); - tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[rs1], -1); - tcg_gen_or_i32(cpu_fpr[rd], cpu_tmp32, cpu_fpr[rs2]); + tcg_gen_orc_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]); break; case 0x078: /* VIS I fsrc2 */ CHECK_FPU_FEATURE(dc, VIS1); @@ -4056,17 +4042,15 @@ static void disas_sparc_insn(DisasContext * dc) break; case 0x07a: /* VIS I fornot1 */ CHECK_FPU_FEATURE(dc, VIS1); - tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs2)], -1); - tcg_gen_or_i32(cpu_fpr[DFPREG(rd)], cpu_tmp32, - cpu_fpr[DFPREG(rs1)]); - tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs2) + 1], -1); - tcg_gen_or_i32(cpu_fpr[DFPREG(rd) + 1], cpu_tmp32, - cpu_fpr[DFPREG(rs1) + 1]); + tcg_gen_orc_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs2)], + cpu_fpr[DFPREG(rs1)]); + tcg_gen_orc_i32(cpu_fpr[DFPREG(rd) + 1], + cpu_fpr[DFPREG(rs2) + 1], + cpu_fpr[DFPREG(rs1) + 1]); break; case 0x07b: /* VIS I fornot1s */ CHECK_FPU_FEATURE(dc, VIS1); - tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[rs2], -1); - tcg_gen_or_i32(cpu_fpr[rd], cpu_tmp32, cpu_fpr[rs1]); + tcg_gen_orc_i32(cpu_fpr[rd], cpu_fpr[rs2], cpu_fpr[rs1]); break; case 0x07c: /* VIS I for */ CHECK_FPU_FEATURE(dc, VIS1); |