From c4c4b32b8112fd06508ca572f564198f1fa34b8e Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Tue, 2 Feb 2010 19:39:11 +0100 Subject: sh7750: handle MMUCR TI bit When the MMUCR TI bit is set, all the UTLB and ITLB entries should be flushed. Signed-off-by: Aurelien Jarno (cherry picked from commit e781d1285fc3b81d689ba25360c6c272116387fa) --- target-sh4/helper.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'target-sh4/helper.c') diff --git a/target-sh4/helper.c b/target-sh4/helper.c index 088d36a5f..e7c494fb9 100644 --- a/target-sh4/helper.c +++ b/target-sh4/helper.c @@ -574,6 +574,24 @@ void cpu_load_tlb(CPUSH4State * env) entry->tc = (uint8_t)cpu_ptea_tc(env->ptea); } + void cpu_sh4_invalidate_tlb(CPUSH4State *s) +{ + int i; + + /* UTLB */ + for (i = 0; i < UTLB_SIZE; i++) { + tlb_t * entry = &s->utlb[i]; + entry->v = 0; + } + /* ITLB */ + for (i = 0; i < UTLB_SIZE; i++) { + tlb_t * entry = &s->utlb[i]; + entry->v = 0; + } + + tlb_flush(s, 1); +} + void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr, uint32_t mem_value) { -- cgit v1.2.3-65-gdbad