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authorAlexey Shvetsov <alexxy@gentoo.org>2013-04-08 22:40:06 +0400
committerAlexey Shvetsov <alexxy@gentoo.org>2013-04-08 22:40:06 +0400
commit1f8b21fa962dedded5bff49c2fe340a11b056970 (patch)
tree2993707b93d8a3ce43b556a674f6058fb5d26f04
parentAdd fixes for clover (diff)
downloadx11-1f8b21fa962dedded5bff49c2fe340a11b056970.tar.gz
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Revert "Add fixes for clover"
This reverts commit 0d15e6b397d74c1a83504ef098494b6b3670583b.
-rw-r--r--media-libs/mesa/files/0001-R600-Add-basic-64-bit-float-load-support-to-GPRs.patch181
-rw-r--r--media-libs/mesa/files/0002-R600-Add-64-bit-v2f32-v2i32-store.patch57
-rw-r--r--media-libs/mesa/files/0003-R600-Add-test-for-64-bit-v2f32-v2i32.patch63
-rw-r--r--media-libs/mesa/mesa-9999.ebuild3
4 files changed, 0 insertions, 304 deletions
diff --git a/media-libs/mesa/files/0001-R600-Add-basic-64-bit-float-load-support-to-GPRs.patch b/media-libs/mesa/files/0001-R600-Add-basic-64-bit-float-load-support-to-GPRs.patch
deleted file mode 100644
index 7e7e4c1b..00000000
--- a/media-libs/mesa/files/0001-R600-Add-basic-64-bit-float-load-support-to-GPRs.patch
+++ /dev/null
@@ -1,181 +0,0 @@
-From ecf4eaedd349d007227f07c145efcd37f4014067 Mon Sep 17 00:00:00 2001
-From: Dmitry Cherkassov <dcherkassov@gmail.com>
-Date: Thu, 7 Mar 2013 20:17:59 +0400
-Subject: [PATCH 1/3] R600: Add basic 64-bit float load support to GPRs
-
-* Added R600_Reg64 class
-* Added T#Index#.XY registers definition
-* Added v2i32 register reads from parameter and global space
-* Added f32 and i32 elements extraction from v2f32 and v2i32
-* Added v2i32 -> v2f32 conversions
-
-Signed-off-by: Dmitry Cherkassov <dcherkassov@gmail.com>
----
- lib/Target/R600/AMDGPUISelLowering.cpp | 3 ++
- lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp | 2 ++
- lib/Target/R600/R600ISelLowering.cpp | 3 ++
- lib/Target/R600/R600Instructions.td | 37 ++++++++++++++++++++++
- lib/Target/R600/R600RegisterInfo.td | 16 ++++++++++
- 5 files changed, 61 insertions(+)
-
-diff --git a/lib/Target/R600/AMDGPUISelLowering.cpp b/lib/Target/R600/AMDGPUISelLowering.cpp
-index a266df5..8c26922 100644
---- a/lib/Target/R600/AMDGPUISelLowering.cpp
-+++ b/lib/Target/R600/AMDGPUISelLowering.cpp
-@@ -60,6 +60,9 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
- setOperationAction(ISD::LOAD, MVT::v4f32, Promote);
- AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32);
-
-+ setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
-+ AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32);
-+
- setOperationAction(ISD::MUL, MVT::i64, Expand);
-
- setOperationAction(ISD::UDIV, MVT::i32, Expand);
-diff --git a/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp b/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp
-index 469a8ad..82fef06 100644
---- a/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp
-+++ b/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp
-@@ -162,9 +162,11 @@ void R600MCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS,
- case AMDGPU::VTX_READ_PARAM_8_eg:
- case AMDGPU::VTX_READ_PARAM_16_eg:
- case AMDGPU::VTX_READ_PARAM_32_eg:
-+ case AMDGPU::VTX_READ_PARAM_64_eg:
- case AMDGPU::VTX_READ_PARAM_128_eg:
- case AMDGPU::VTX_READ_GLOBAL_8_eg:
- case AMDGPU::VTX_READ_GLOBAL_32_eg:
-+ case AMDGPU::VTX_READ_GLOBAL_64_eg:
- case AMDGPU::VTX_READ_GLOBAL_128_eg:
- case AMDGPU::TEX_VTX_CONSTBUF:
- case AMDGPU::TEX_VTX_TEXBUF : {
-diff --git a/lib/Target/R600/R600ISelLowering.cpp b/lib/Target/R600/R600ISelLowering.cpp
-index 53e6e51..953f22d 100644
---- a/lib/Target/R600/R600ISelLowering.cpp
-+++ b/lib/Target/R600/R600ISelLowering.cpp
-@@ -32,6 +32,9 @@ R600TargetLowering::R600TargetLowering(TargetMachine &TM) :
- addRegisterClass(MVT::f32, &AMDGPU::R600_Reg32RegClass);
- addRegisterClass(MVT::v4i32, &AMDGPU::R600_Reg128RegClass);
- addRegisterClass(MVT::i32, &AMDGPU::R600_Reg32RegClass);
-+ addRegisterClass(MVT::v2f32, &AMDGPU::R600_Reg64RegClass);
-+ addRegisterClass(MVT::v2i32, &AMDGPU::R600_Reg64RegClass);
-+
- computeRegisterProperties();
-
- setOperationAction(ISD::FADD, MVT::v4f32, Expand);
-diff --git a/lib/Target/R600/R600Instructions.td b/lib/Target/R600/R600Instructions.td
-index b4c45e1..716c90d 100644
---- a/lib/Target/R600/R600Instructions.td
-+++ b/lib/Target/R600/R600Instructions.td
-@@ -1824,6 +1824,18 @@ class VTX_READ_32_eg <bits<8> buffer_id, list<dag> pattern>
- let Constraints = "$ptr.ptr = $dst";
- }
-
-+class VTX_READ_64_eg <bits<8> buffer_id, list<dag> pattern>
-+ : VTX_READ_eg <"VTX_READ_64", buffer_id, (outs R600_Reg64:$dst),
-+ pattern> {
-+
-+ let MEGA_FETCH_COUNT = 8;
-+ let DST_SEL_X = 0;
-+ let DST_SEL_Y = 1;
-+ let DST_SEL_Z = 7;
-+ let DST_SEL_W = 7;
-+ let DATA_FORMAT = 0x1D; // COLOR_32_32
-+}
-+
- class VTX_READ_128_eg <bits<8> buffer_id, list<dag> pattern>
- : VTX_READ_eg <"VTX_READ_128", buffer_id, (outs R600_Reg128:$dst),
- pattern> {
-@@ -1857,6 +1869,11 @@ def VTX_READ_PARAM_32_eg : VTX_READ_32_eg <0,
- [(set (i32 R600_TReg32_X:$dst), (load_param ADDRVTX_READ:$ptr))]
- >;
-
-+def VTX_READ_PARAM_64_eg : VTX_READ_64_eg <0,
-+ [(set (v2i32 R600_Reg64:$dst), (load_param ADDRVTX_READ:$ptr))]
-+>;
-+
-+
- def VTX_READ_PARAM_128_eg : VTX_READ_128_eg <0,
- [(set (v4i32 R600_Reg128:$dst), (load_param ADDRVTX_READ:$ptr))]
- >;
-@@ -1875,6 +1892,12 @@ def VTX_READ_GLOBAL_32_eg : VTX_READ_32_eg <1,
- [(set (i32 R600_TReg32_X:$dst), (global_load ADDRVTX_READ:$ptr))]
- >;
-
-+// 64-bit reads
-+def VTX_READ_GLOBAL_64_eg : VTX_READ_64_eg <1,
-+ [(set (v2i32 R600_Reg64:$dst), (global_load ADDRVTX_READ:$ptr))]
-+>;
-+
-+
- // 128-bit reads
- def VTX_READ_GLOBAL_128_eg : VTX_READ_128_eg <1,
- [(set (v4i32 R600_Reg128:$dst), (global_load ADDRVTX_READ:$ptr))]
-@@ -2352,10 +2375,24 @@ def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 3, sub3>;
- def : Vector4_Build <v4f32, R600_Reg128, f32, R600_Reg32>;
- def : Vector4_Build <v4i32, R600_Reg128, i32, R600_Reg32>;
-
-+def : Extract_Element <f32, v2f32, R600_Reg64, 0, sub0>;
-+def : Extract_Element <f32, v2f32, R600_Reg64, 1, sub1>;
-+
-+def : Insert_Element <f32, v2f32, R600_Reg32, R600_Reg64, 0, sub0>;
-+def : Insert_Element <f32, v2f32, R600_Reg32, R600_Reg64, 1, sub1>;
-+
-+def : Extract_Element <i32, v2i32, R600_Reg64, 0, sub0>;
-+def : Extract_Element <i32, v2i32, R600_Reg64, 1, sub1>;
-+
-+def : Insert_Element <i32, v2i32, R600_Reg32, R600_Reg64, 0, sub0>;
-+def : Insert_Element <i32, v2i32, R600_Reg32, R600_Reg64, 1, sub1>;
-+
- // bitconvert patterns
-
- def : BitConvert <i32, f32, R600_Reg32>;
- def : BitConvert <f32, i32, R600_Reg32>;
-+def : BitConvert <v2f32, v2i32, R600_Reg64>;
-+def : BitConvert <v2i32, v2f32, R600_Reg64>;
- def : BitConvert <v4f32, v4i32, R600_Reg128>;
- def : BitConvert <v4i32, v4f32, R600_Reg128>;
-
-diff --git a/lib/Target/R600/R600RegisterInfo.td b/lib/Target/R600/R600RegisterInfo.td
-index 03f4976..33593bc 100644
---- a/lib/Target/R600/R600RegisterInfo.td
-+++ b/lib/Target/R600/R600RegisterInfo.td
-@@ -23,6 +23,14 @@ class R600Reg_128<string n, list<Register> subregs, bits<16> encoding> :
- let HWEncoding = encoding;
- }
-
-+class R600Reg_64<string n, list<Register> subregs, bits<16> encoding> :
-+ RegisterWithSubRegs<n, subregs> {
-+ let Namespace = "AMDGPU";
-+ let SubRegIndices = [sub0, sub1];
-+ let HWEncoding = encoding;
-+}
-+
-+
- foreach Index = 0-127 in {
- foreach Chan = [ "X", "Y", "Z", "W" ] in {
- // 32-bit Temporary Registers
-@@ -41,6 +49,11 @@ foreach Index = 0-127 in {
- !cast<Register>("T"#Index#"_Z"),
- !cast<Register>("T"#Index#"_W")],
- Index>;
-+
-+ def T#Index#_XY : R600Reg_64 <"T"#Index#".XY",
-+ [!cast<Register>("T"#Index#"_X"),
-+ !cast<Register>("T"#Index#"_Y")],
-+ Index>;
- }
-
- // KCACHE_BANK0
-@@ -178,6 +191,9 @@ def R600_Reg128 : RegisterClass<"AMDGPU", [v4f32, v4i32], 128,
- let CopyCost = -1;
- }
-
-+def R600_Reg64 : RegisterClass<"AMDGPU", [v2f32, v2i32], 64,
-+ (add (sequence "T%u_XY", 0, 63))>;
-+
- //===----------------------------------------------------------------------===//
- // Register classes for indirect addressing
- //===----------------------------------------------------------------------===//
---
-1.8.1.5
-
diff --git a/media-libs/mesa/files/0002-R600-Add-64-bit-v2f32-v2i32-store.patch b/media-libs/mesa/files/0002-R600-Add-64-bit-v2f32-v2i32-store.patch
deleted file mode 100644
index b51bb0f7..00000000
--- a/media-libs/mesa/files/0002-R600-Add-64-bit-v2f32-v2i32-store.patch
+++ /dev/null
@@ -1,57 +0,0 @@
-From f48f6462adc38526a710626743863ba3915c68b4 Mon Sep 17 00:00:00 2001
-From: Dmitry Cherkassov <dcherkassov@gmail.com>
-Date: Thu, 7 Mar 2013 20:18:00 +0400
-Subject: [PATCH 2/3] R600: Add 64-bit v2f32/v2i32 store
-
-Signed-off-by: Dmitry Cherkassov <dcherkassov@gmail.com>
----
- lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp | 1 +
- lib/Target/R600/R600ISelLowering.cpp | 1 +
- lib/Target/R600/R600Instructions.td | 7 +++++++
- 3 files changed, 9 insertions(+)
-
-diff --git a/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp b/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp
-index 82fef06..e529f76 100644
---- a/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp
-+++ b/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp
-@@ -152,6 +152,7 @@ void R600MCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS,
- break;
- }
- case AMDGPU::RAT_WRITE_CACHELESS_32_eg:
-+ case AMDGPU::RAT_WRITE_CACHELESS_64_eg:
- case AMDGPU::RAT_WRITE_CACHELESS_128_eg: {
- uint64_t inst = getBinaryCodeForInstr(MI, Fixups);
- EmitByte(INSTR_NATIVE, OS);
-diff --git a/lib/Target/R600/R600ISelLowering.cpp b/lib/Target/R600/R600ISelLowering.cpp
-index 953f22d..9980fe1 100644
---- a/lib/Target/R600/R600ISelLowering.cpp
-+++ b/lib/Target/R600/R600ISelLowering.cpp
-@@ -160,6 +160,7 @@ MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
- }
-
- case AMDGPU::RAT_WRITE_CACHELESS_32_eg:
-+ case AMDGPU::RAT_WRITE_CACHELESS_64_eg:
- case AMDGPU::RAT_WRITE_CACHELESS_128_eg: {
- unsigned EOP = (llvm::next(I)->getOpcode() == AMDGPU::RETURN) ? 1 : 0;
-
-diff --git a/lib/Target/R600/R600Instructions.td b/lib/Target/R600/R600Instructions.td
-index 716c90d..8c926cd 100644
---- a/lib/Target/R600/R600Instructions.td
-+++ b/lib/Target/R600/R600Instructions.td
-@@ -1719,6 +1719,13 @@ def RAT_WRITE_CACHELESS_32_eg : RAT_WRITE_CACHELESS_eg <
- [(global_store (i32 R600_TReg32_X:$rw_gpr), R600_TReg32_X:$index_gpr)]
- >;
-
-+// 64-bit store
-+def RAT_WRITE_CACHELESS_64_eg : RAT_WRITE_CACHELESS_eg <
-+ (ins R600_Reg64:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop),
-+ 0x3, "RAT_WRITE_CACHELESS_64_eg",
-+ [(global_store (v2i32 R600_Reg64:$rw_gpr), R600_TReg32_X:$index_gpr)]
-+>;
-+
- //128-bit store
- def RAT_WRITE_CACHELESS_128_eg : RAT_WRITE_CACHELESS_eg <
- (ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop),
---
-1.8.1.5
-
diff --git a/media-libs/mesa/files/0003-R600-Add-test-for-64-bit-v2f32-v2i32.patch b/media-libs/mesa/files/0003-R600-Add-test-for-64-bit-v2f32-v2i32.patch
deleted file mode 100644
index 13511a30..00000000
--- a/media-libs/mesa/files/0003-R600-Add-test-for-64-bit-v2f32-v2i32.patch
+++ /dev/null
@@ -1,63 +0,0 @@
-From d01a8de8442b2ee3b7b49fb9cb5cb39d238116f6 Mon Sep 17 00:00:00 2001
-From: Dmitry Cherkassov <dcherkassov@gmail.com>
-Date: Thu, 7 Mar 2013 20:18:01 +0400
-Subject: [PATCH 3/3] R600: Add test for 64-bit v2f32/v2i32
-
-Added tests for checking v2f32/v2i32 load, store and element extract
-
-Signed-off-by: Dmitry Cherkassov <dcherkassov@gmail.com>
----
- test/CodeGen/R600/64bit-kernel-args.ll | 41 ++++++++++++++++++++++++++++++++++
- 1 file changed, 41 insertions(+)
- create mode 100644 test/CodeGen/R600/64bit-kernel-args.ll
-
-diff --git a/test/CodeGen/R600/64bit-kernel-args.ll b/test/CodeGen/R600/64bit-kernel-args.ll
-new file mode 100644
-index 0000000..fe86fcf
---- /dev/null
-+++ b/test/CodeGen/R600/64bit-kernel-args.ll
-@@ -0,0 +1,41 @@
-+;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
-+
-+; CHECK: @v2i32_kernel_arg
-+; CHECK: VTX_READ_64 T{{[0-9]+}}.XY, T{{[0-9]+}}.X, 40
-+define void @v2i32_load_extract_store(i32 addrspace(1)* nocapture %out, <2 x i32> %in) {
-+entry:
-+ %0 = extractelement <2 x i32> %in, i32 0
-+ store i32 %0, i32 addrspace(1)* %out, align 4
-+ %1 = extractelement <2 x i32> %in, i32 1
-+ %arrayidx1 = getelementptr inbounds i32 addrspace(1)* %out, i32 1
-+ store i32 %1, i32 addrspace(1)* %arrayidx1, align 4
-+ ret void
-+}
-+
-+; CHECK: @v2f32_kernel_arg
-+; CHECK: VTX_READ_64 T{{[0-9]+}}.XY, T{{[0-9]+}}.X, 40
-+define void @v2f32_load_extract_store(float addrspace(1)* nocapture %out, <2 x float> %in) {
-+entry:
-+ %0 = extractelement <2 x float> %in, i32 0
-+ store float %0, float addrspace(1)* %out, align 4
-+ %1 = extractelement <2 x float> %in, i32 1
-+ %arrayidx1 = getelementptr inbounds float addrspace(1)* %out, i32 1
-+ store float %1, float addrspace(1)* %arrayidx1, align 4
-+ ret void
-+}
-+
-+; CHECK: @v2i32_kernel_arg
-+; CHECK: VTX_READ_64 T{{[0-9]+}}.XY, T{{[0-9]+}}.X, 40
-+define void @v2i32_load_store(<2 x i32> addrspace(1)* %out, <2 x i32> %in) {
-+entry:
-+ store <2 x i32> %in, <2 x i32> addrspace(1)* %out
-+ ret void
-+}
-+
-+; CHECK: @v2f32_kernel_arg
-+; CHECK: VTX_READ_64 T{{[0-9]+}}.XY, T{{[0-9]+}}.X, 40
-+define void @v2f32_load_store(<2 x float> addrspace(1)* %out, <2 x float> %in) {
-+entry:
-+ store <2 x float> %in, <2 x float> addrspace(1)* %out
-+ ret void
-+}
---
-1.8.1.5
-
diff --git a/media-libs/mesa/mesa-9999.ebuild b/media-libs/mesa/mesa-9999.ebuild
index d74726c3..f679276e 100644
--- a/media-libs/mesa/mesa-9999.ebuild
+++ b/media-libs/mesa/mesa-9999.ebuild
@@ -174,9 +174,6 @@ src_prepare() {
# use non-NULL platform id
epatch "${FILESDIR}/${P}-clover-use-non-null-platform-id.patch"
- epatch "${FILESDIR}/0001-R600-Add-basic-64-bit-float-load-support-to-GPRs.patch"
- epatch "${FILESDIR}/0002-R600-Add-64-bit-v2f32-v2i32-store.patch"
- epatch "${FILESDIR}/0003-R600-Add-test-for-64-bit-v2f32-v2i32.patch"
# fix for hardened pax_kernel, bug 240956
[[ ${PV} != 9999* ]] && epatch "${FILESDIR}"/glx_ro_text_segm.patch