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authorHuang Rui <vowstar@gmail.com>2019-12-23 10:45:38 +0800
committerJoonas Niilola <juippis@gentoo.org>2020-01-05 12:09:45 +0200
commit4bbf7865096bfbbeb861ac51585e6fb3ba9f6ded (patch)
tree53832e23baeb7301df2c2214860cfc01608d12a4 /sci-electronics/iverilog
parentdev-python/libsass: add two missing deps (diff)
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sci-electronics/iverilog: bump to 10.3
Bump iverilog version to 10.3 Follow these URL: * http://iverilog.icarus.com * https://github.com/steveicarus/iverilog Update LICENSE to LGPL-2.1 Rewrite ebuild to download file from iverilog official github repo Update maintainer list, add proxy-maint Add github upstream https://github.com/steveicarus/iverilog Bump the version with bugfixes Replace autoconf.sh to make it utilize the autotools eclass Fix upstream parallel compilation bug Add https://github.com/steveicarus/iverilog in HOMEPAGE array Happy new year 2020 Tested from my overlay: https://github.com/vowstar/vowstar-overlay/ Closes: https://bugs.gentoo.org/687080 Closes: https://bugs.gentoo.org/701122 Closes: https://bugs.gentoo.org/704344 Package-Manager: Portage-2.3.82, Repoman-2.3.20 Signed-off-by: Huang Rui <vowstar@gmail.com> Closes: https://github.com/gentoo/gentoo/pull/14096 Signed-off-by: Joonas Niilola <juippis@gentoo.org>
Diffstat (limited to 'sci-electronics/iverilog')
-rw-r--r--sci-electronics/iverilog/Manifest1
-rw-r--r--sci-electronics/iverilog/iverilog-10.3.ebuild68
-rw-r--r--sci-electronics/iverilog/metadata.xml31
3 files changed, 90 insertions, 10 deletions
diff --git a/sci-electronics/iverilog/Manifest b/sci-electronics/iverilog/Manifest
index 2459fd7d45c..19e0b1a4411 100644
--- a/sci-electronics/iverilog/Manifest
+++ b/sci-electronics/iverilog/Manifest
@@ -1,3 +1,4 @@
+DIST iverilog-10.3.tar.gz 1600835 BLAKE2B 107c57c61fb27c18f4020f7853bf6ca83d1a86fdc73c57ea207828baf6b7a26d42e43ce7b33580f050a4c0b8f63bca6accecf678323a3bbbee1eb9c1d8fa2caa SHA512 67076e19a208576c21a0462ff7d15d00a9d47740c47518a5523bd928b3118360d85eb84c317963717d15e5246ece3727259f6ff3baf59e195340530cc9086a1d
DIST verilog-0.9.6.tar.gz 1219982 BLAKE2B 12f7dfb1ab8b7e4524cf0a3061ce801bfa741015fc1446aef7ffe51c42d76b5d0578e78ce13cd8c3fb6bac580e9da1ed11ca03e1fd02f8cb75dd74425546f851 SHA512 63c18f211eb9711547db65b859551063129cf18acb1196eaa88562f194231079fe929a6f7b8fbe2160863c521f02dde079e792f1b0bbe1c2514deafd55d5288c
DIST verilog-0.9.7.tar.gz 1238088 BLAKE2B c0b173b4857abc0d35ad05d9f11d5265763c92e625aadb1b487978c40e0679725b8e6de0fc05cc8e4bc7a6db6e1d9abacf886942b05e27d8513b9586cca156f9 SHA512 1a81f132c667f5cd33a11156364a366806ef9b6ef59b86f69df852af79cc92db17df8db0bace4e3c14929b0110df0aa7d83f35f664057e715842acf7bd21c1f5
DIST verilog-10.2.tar.gz 1695227 BLAKE2B ea2488de55ef60a248e7f5ffd5e06c6d86d57f3cff4536cb64a727ab70d8868847e53beec093e21243a1e81ede021b0ccde771d66ce1d986f737b5d925aaff11 SHA512 21e0861ee994daf0a98d0da3e0ad665e37cba4669faa873ae57d05eb41794b6cc2948c88cc07ebe1e9266850ad2bad189096ae6911b9c4064f772279d0901aef
diff --git a/sci-electronics/iverilog/iverilog-10.3.ebuild b/sci-electronics/iverilog/iverilog-10.3.ebuild
new file mode 100644
index 00000000000..145ceb786d7
--- /dev/null
+++ b/sci-electronics/iverilog/iverilog-10.3.ebuild
@@ -0,0 +1,68 @@
+# Copyright 1999-2020 Gentoo Authors
+# Distributed under the terms of the GNU General Public License v2
+
+EAPI=7
+
+inherit autotools
+
+GITHUB_PV=$(ver_rs 1- '_')
+
+DESCRIPTION="A Verilog simulation and synthesis tool"
+HOMEPAGE="
+ http://iverilog.icarus.com
+ https://github.com/steveicarus/iverilog
+"
+
+if [[ ${PV} == "9999" ]] ; then
+ inherit git-r3
+ EGIT_REPO_URI="https://github.com/steveicarus/${PN}.git"
+else
+ SRC_URI="https://github.com/steveicarus/${PN}/archive/v${GITHUB_PV}.tar.gz -> ${P}.tar.gz"
+ KEYWORDS="~alpha ~amd64 ~arm ~arm64 ~hppa ~ia64 ~m68k ~mips ~ppc ~ppc64 ~riscv ~s390 ~sh ~sparc ~x86"
+ S="${WORKDIR}/${PN}-${GITHUB_PV}"
+fi
+
+LICENSE="LGPL-2.1"
+SLOT="0"
+IUSE="examples"
+
+# If you are building from git, you will also need gperf to generate
+# the configure scripts.
+RDEPEND="
+ sys-libs/readline:0
+ sys-libs/zlib
+"
+
+DEPEND="
+ dev-util/gperf
+ ${RDEPEND}
+"
+
+src_prepare() {
+ default
+
+ # From upstreams autoconf.sh, to make it utilize the autotools eclass
+ # Here translate the autoconf.sh, equivalent to the following code
+ # > sh autoconf.sh
+
+ # Fix build fail problem when using large job number, make it parallel safe
+ echo ".NOTPARALLEL: install" >> ./Makefile.in || die
+
+ # Autoconf in root ...
+ eautoconf --force
+ # Precompiling lexor_keyword.gperf
+ gperf -o -i 7 -C -k 1-4,6,9,\$ -H keyword_hash -N check_identifier -t ./lexor_keyword.gperf > lexor_keyword.cc || die
+ # Precompiling vhdlpp/lexor_keyword.gperf
+ cd vhdlpp || die
+ gperf -o -i 7 --ignore-case -C -k 1-4,6,9,\$ -H keyword_hash -N check_identifier -t ./lexor_keyword.gperf > lexor_keyword.cc || die
+}
+
+src_install() {
+ local DOCS=( *.txt )
+ default
+
+ if use examples; then
+ dodoc -r examples
+ docompress -x /usr/share/doc/${PF}/examples
+ fi
+}
diff --git a/sci-electronics/iverilog/metadata.xml b/sci-electronics/iverilog/metadata.xml
index 21d969b3bbd..edc7fde50a3 100644
--- a/sci-electronics/iverilog/metadata.xml
+++ b/sci-electronics/iverilog/metadata.xml
@@ -1,14 +1,25 @@
<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE pkgmetadata SYSTEM "http://www.gentoo.org/dtd/metadata.dtd">
<pkgmetadata>
- <maintainer type="project">
- <email>sci-electronics@gentoo.org</email>
- <name>Gentoo Electronics Project</name>
- </maintainer>
- <longdescription>
- Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a
- compiler, compiling source code writen in Verilog (IEEE-1364) into some target
- format. The compiler proper is intended to parse and elaborate design
- descriptions written to the IEEE standard IEEE Std 1364-2001.
- </longdescription>
+ <maintainer type="person">
+ <email>vowstar@gmail.com</email>
+ <name>Huang Rui</name>
+ </maintainer>
+ <maintainer type="project">
+ <email>sci-electronics@gentoo.org</email>
+ <name>Gentoo Electronics Project</name>
+ </maintainer>
+ <maintainer type="project">
+ <email>proxy-maint@gentoo.org</email>
+ <name>Proxy Maintainers</name>
+ </maintainer>
+ <upstream>
+ <remote-id type="github">steveicarus/iverilog</remote-id>
+ </upstream>
+ <longdescription>
+ Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a
+ compiler, compiling source code writen in Verilog (IEEE-1364) into some target
+ format. The compiler proper is intended to parse and elaborate design
+ descriptions written to the IEEE standard IEEE Std 1364-2001.
+ </longdescription>
</pkgmetadata>