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-rw-r--r--sci-electronics/vbs/Manifest1
-rw-r--r--sci-electronics/vbs/files/vbs-1.4.0-gcc-4.1.patch111
-rw-r--r--sci-electronics/vbs/files/vbs-1.4.0-gcc-4.3.patch30
-rw-r--r--sci-electronics/vbs/metadata.xml10
-rw-r--r--sci-electronics/vbs/vbs-1.4.0.ebuild42
5 files changed, 194 insertions, 0 deletions
diff --git a/sci-electronics/vbs/Manifest b/sci-electronics/vbs/Manifest
new file mode 100644
index 00000000000..fab6d3a535f
--- /dev/null
+++ b/sci-electronics/vbs/Manifest
@@ -0,0 +1 @@
+DIST vbs-1.4.0.tar.gz 275974 RMD160 a008225ab72b92f922b2f769bd13beca0b82530c SHA1 fd39003417230d8d4cb12b8ff1e005006b6c8946 SHA256 c29e6d2bb89ef9e08f8b94eadd06801c79bae7fcb401748d8a2ef28d742e80b4
diff --git a/sci-electronics/vbs/files/vbs-1.4.0-gcc-4.1.patch b/sci-electronics/vbs/files/vbs-1.4.0-gcc-4.1.patch
new file mode 100644
index 00000000000..20f2aadb7e6
--- /dev/null
+++ b/sci-electronics/vbs/files/vbs-1.4.0-gcc-4.1.patch
@@ -0,0 +1,111 @@
+diff -ur vbs-1.4.0.orig/src/common/bvector.h vbs-1.4.0/src/common/bvector.h
+--- vbs-1.4.0.orig/src/common/bvector.h 2003-01-12 05:40:59.000000000 +0100
++++ vbs-1.4.0/src/common/bvector.h 2007-03-09 22:40:02.000000000 +0100
+@@ -90,9 +90,9 @@
+ size_type _size; // Size of this sub-bit vector.
+
+ // Only bit_vector can create a sub_bit_vector object.
++ public:
+ sub_bit_vector(bit_vector &, const position_type, const position_type);
+ sub_bit_vector(const sub_bit_vector &);
+- public:
+ sub_bit_vector &operator=(const sub_bit_vector &);
+ sub_bit_vector &operator=(const const_sub_bit_vector &);
+ sub_bit_vector &operator=(const bit_vector &);
+@@ -116,8 +116,8 @@
+
+ // Only bit_vector can create a sub_bit_vector object.
+ const_sub_bit_vector(const bit_vector &, const position_type, const position_type);
+- const_sub_bit_vector(const const_sub_bit_vector &);
+ public:
++ const_sub_bit_vector(const const_sub_bit_vector &);
+ size_type size() const
+ { return _size; }
+ ostream_type &info(ostream_type &) const;
+diff -ur vbs-1.4.0.orig/src/common/logic.h vbs-1.4.0/src/common/logic.h
+--- vbs-1.4.0.orig/src/common/logic.h 2002-10-21 11:01:02.000000000 +0200
++++ vbs-1.4.0/src/common/logic.h 2007-03-09 22:40:02.000000000 +0100
+@@ -44,6 +44,10 @@
+ { return (_state == HI) ? true : false; }
+ operator int() const
+ { return _state; }
++
++ operator long int() const
++ { return _state; }
++
+ operator char() const
+ {
+ switch (_state)
+diff -ur vbs-1.4.0.orig/src/common/st_net.h vbs-1.4.0/src/common/st_net.h
+--- vbs-1.4.0.orig/src/common/st_net.h 2002-11-24 03:07:00.000000000 +0100
++++ vbs-1.4.0/src/common/st_net.h 2007-03-09 22:40:02.000000000 +0100
+@@ -133,4 +133,7 @@
+ const st_net &_net;
+ };
+
++void entry_iovars(st_net::io_list &, st_net::arg_list &);
++void exit_iovars(st_net::io_list &, st_net::arg_list &);
++
+ #endif // _ST_NET_H
+diff -ur vbs-1.4.0.orig/src/expr/erdwr.cc vbs-1.4.0/src/expr/erdwr.cc
+--- vbs-1.4.0.orig/src/expr/erdwr.cc 2002-05-28 08:22:46.000000000 +0200
++++ vbs-1.4.0/src/expr/erdwr.cc 2007-03-09 22:40:02.000000000 +0100
+@@ -25,8 +25,9 @@
+ expr_base *
+ read_expr::operator()() const
+ {
+- VBSOBJ_EXPR_TYPE type;
+- _in >> (int &) type;
++ int type_num = 0;
++ _in >> type_num;
++ VBSOBJ_EXPR_TYPE type = VBSOBJ_EXPR_TYPE(type_num);
+ long ln;
+ _in >> ln;
+ expr_base *expr = 0;
+diff -ur vbs-1.4.0.orig/src/Makefile.in vbs-1.4.0/src/Makefile.in
+--- vbs-1.4.0.orig/src/Makefile.in 2003-06-08 00:38:24.000000000 +0200
++++ vbs-1.4.0/src/Makefile.in 2007-03-09 22:40:02.000000000 +0100
+@@ -329,13 +329,15 @@
+ rm -f *.o
+ rm -f *.a
+ rm -f *.so
++ rm -f vbs
+
+ clean-repo:
+ if test -d ptrepository; then rm -rf ptrepository; fi
+ rm -f *.rpo
+
+ install:
+- $(INSTALL) vbs $(bindir)
++ $(INSTALL) -d $(DESTDIR)$(bindir)
++ $(INSTALL) vbs $(DESTDIR)$(bindir)
+
+ tarball:
+ @echo "===== Tar ball ======"
+diff -ur vbs-1.4.0.orig/src/misc/mrdwr.cc vbs-1.4.0/src/misc/mrdwr.cc
+--- vbs-1.4.0.orig/src/misc/mrdwr.cc 2002-05-28 11:42:00.000000000 +0200
++++ vbs-1.4.0/src/misc/mrdwr.cc 2007-03-09 22:40:02.000000000 +0100
+@@ -21,8 +21,9 @@
+ module *
+ read_module::operator()() const
+ {
+- VBSOBJ_MISC_TYPE type;
+- _in >> (int &) type;
++ int type_num = 0;
++ _in >> type_num;
++ VBSOBJ_MISC_TYPE type = VBSOBJ_MISC_TYPE(type_num);
+ if (type != VBSOBJ_MISC_MODULE)
+ {
+ vbs_err.set_data(vbs_error::SE_VBSOBJ, -1);
+@@ -129,8 +130,9 @@
+ port *
+ read_port::operator()() const
+ {
+- VBSOBJ_MISC_TYPE type;
+- _in >> (int &) type;
++ int type_num = 0;
++ _in >> type_num;
++ VBSOBJ_MISC_TYPE type = VBSOBJ_MISC_TYPE(type_num);
+ if (type != VBSOBJ_MISC_PORT)
+ {
+ vbs_err.set_data(vbs_error::SE_VBSOBJ, -1);
diff --git a/sci-electronics/vbs/files/vbs-1.4.0-gcc-4.3.patch b/sci-electronics/vbs/files/vbs-1.4.0-gcc-4.3.patch
new file mode 100644
index 00000000000..c0a62e1d0e2
--- /dev/null
+++ b/sci-electronics/vbs/files/vbs-1.4.0-gcc-4.3.patch
@@ -0,0 +1,30 @@
+--- vbs-1.4.0b/src/common/dumpstrm.cc 2009-01-21 02:42:43.000000000 -0400
++++ vbs-1.4.0/src/common/dumpstrm.cc 2009-01-21 02:48:57.000000000 -0400
+@@ -13,6 +13,7 @@
+
+ #include <cstdio> // sprintf
+ #include <iostream>
++#include <cstdlib>
+ #include "dumpstrm.h"
+
+ using std::cerr;
+--- vbs-1.4.0b/src/common/logic.h 2009-01-21 02:42:43.000000000 -0400
++++ vbs-1.4.0/src/common/logic.h 2009-01-21 02:48:05.000000000 -0400
+@@ -18,6 +18,7 @@
+
+ #ifndef _LOGIC_H
+ #define _LOGIC_H
++#include <cstdlib>
+
+ class logic
+ {
+--- vbs-1.4.0b/src/common/bvector.h 2009-01-21 02:42:43.000000000 -0400
++++ vbs-1.4.0/src/common/bvector.h 2009-01-21 02:46:31.000000000 -0400
+@@ -30,6 +30,7 @@
+ #include <string>
+ #include <utility>
+ #include <iostream>
++#include <cstring>
+ #include "common/logic.h"
+
+ class bit_vector
diff --git a/sci-electronics/vbs/metadata.xml b/sci-electronics/vbs/metadata.xml
new file mode 100644
index 00000000000..38fa0bd5549
--- /dev/null
+++ b/sci-electronics/vbs/metadata.xml
@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE pkgmetadata SYSTEM "http://www.gentoo.org/dtd/metadata.dtd">
+<pkgmetadata>
+ <herd>sci-electronics</herd>
+ <longdescription>
+ This program is a simple implementation of a Verilog simulator. VBS tries to
+ implement all of the Verilog behavioral constructs that are synthesizable, but
+ still allow complex test vectors for simulation.
+ </longdescription>
+</pkgmetadata>
diff --git a/sci-electronics/vbs/vbs-1.4.0.ebuild b/sci-electronics/vbs/vbs-1.4.0.ebuild
new file mode 100644
index 00000000000..913aebb2565
--- /dev/null
+++ b/sci-electronics/vbs/vbs-1.4.0.ebuild
@@ -0,0 +1,42 @@
+# Copyright 1999-2012 Gentoo Foundation
+# Distributed under the terms of the GNU General Public License v2
+# $Id$
+
+EAPI="2"
+
+inherit eutils
+
+HOMEPAGE="http://www.geda.seul.org/tools/vbs/index.html"
+DESCRIPTION="vbs - the Verilog Behavioral Simulator"
+SRC_URI="http://www.geda.seul.org/dist/${P}.tar.gz"
+
+SLOT="0"
+LICENSE="GPL-2"
+IUSE="examples"
+KEYWORDS="~amd64 ppc ~x86"
+
+DEPEND=">=sys-devel/flex-2.3
+ >=sys-devel/bison-1.22"
+RDEPEND=""
+
+S="${WORKDIR}/${P}/src"
+
+src_prepare() {
+ epatch "${FILESDIR}/${P}-gcc-4.1.patch"
+ epatch "${FILESDIR}/${P}-gcc-4.3.patch"
+ sed -i -e "s/strrchr(n,'.')/const_cast<char*>(strrchr(n,'.'))/" common/scp_tab.cc || die "sed failed"
+}
+
+src_compile() {
+ emake -j1 vbs || die "Compilation failed"
+}
+
+src_install() {
+ dobin vbs
+ cd ..
+ dodoc BUGS CHANGELOG* CONTRIBUTORS COPYRIGHT FAQ README vbs.txt
+ if use examples ; then
+ insinto /usr/share/${PF}/examples
+ doins EXAMPLES/*
+ fi
+}