From 56bd759df1d0c750a065b8c845e93d5dfa6b549d Mon Sep 17 00:00:00 2001 From: "Robin H. Johnson" Date: Sat, 8 Aug 2015 13:49:04 -0700 Subject: proj/gentoo: Initial commit MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This commit represents a new era for Gentoo: Storing the gentoo-x86 tree in Git, as converted from CVS. This commit is the start of the NEW history. Any historical data is intended to be grafted onto this point. Creation process: 1. Take final CVS checkout snapshot 2. Remove ALL ChangeLog* files 3. Transform all Manifests to thin 4. Remove empty Manifests 5. Convert all stale $Header$/$Id$ CVS keywords to non-expanded Git $Id$ 5.1. Do not touch files with -kb/-ko keyword flags. Signed-off-by: Robin H. Johnson X-Thanks: Alec Warner - did the GSoC 2006 migration tests X-Thanks: Robin H. Johnson - infra guy, herding this project X-Thanks: Nguyen Thai Ngoc Duy - Former Gentoo developer, wrote Git features for the migration X-Thanks: Brian Harring - wrote much python to improve cvs2svn X-Thanks: Rich Freeman - validation scripts X-Thanks: Patrick Lauer - Gentoo dev, running new 2014 work in migration X-Thanks: Michał Górny - scripts, QA, nagging X-Thanks: All of other Gentoo developers - many ideas and lots of paint on the bikeshed --- sci-electronics/iverilog/Manifest | 2 + .../iverilog/files/iverilog-0.9.1-gcc45.patch | 37 ++++++++++++++++ sci-electronics/iverilog/iverilog-0.9.6.ebuild | 50 ++++++++++++++++++++++ sci-electronics/iverilog/iverilog-0.9.7.ebuild | 50 ++++++++++++++++++++++ sci-electronics/iverilog/metadata.xml | 11 +++++ 5 files changed, 150 insertions(+) create mode 100644 sci-electronics/iverilog/Manifest create mode 100644 sci-electronics/iverilog/files/iverilog-0.9.1-gcc45.patch create mode 100644 sci-electronics/iverilog/iverilog-0.9.6.ebuild create mode 100644 sci-electronics/iverilog/iverilog-0.9.7.ebuild create mode 100644 sci-electronics/iverilog/metadata.xml (limited to 'sci-electronics/iverilog') diff --git a/sci-electronics/iverilog/Manifest b/sci-electronics/iverilog/Manifest new file mode 100644 index 000000000000..75c6277dfa1b --- /dev/null +++ b/sci-electronics/iverilog/Manifest @@ -0,0 +1,2 @@ +DIST verilog-0.9.6.tar.gz 1219982 SHA256 25304d5d58d6411fcd1ab94992a505215eea5a6bbd9779c2be2d9d19f38cd54a SHA512 63c18f211eb9711547db65b859551063129cf18acb1196eaa88562f194231079fe929a6f7b8fbe2160863c521f02dde079e792f1b0bbe1c2514deafd55d5288c WHIRLPOOL 137e94edde19f591214847bb729368a8158a0275f3a88cbb1637bf05689cf3cf765a3db429e282b321861b536e7b2059b52390ca0da9f8e9530ea124cedd0cc9 +DIST verilog-0.9.7.tar.gz 1238088 SHA256 7a5e72e17bfb4c3a59264d8f3cc4e70a7c49c1307173348fdd44e079388e7454 SHA512 1a81f132c667f5cd33a11156364a366806ef9b6ef59b86f69df852af79cc92db17df8db0bace4e3c14929b0110df0aa7d83f35f664057e715842acf7bd21c1f5 WHIRLPOOL 4cf808b0fff6d8498a2188785dc8a3befd0272da1e90a02cd767c700074a002de8262c1873e4f16523f527bbb871d50f049d552bb142b2ae7471282c26bc57d0 diff --git a/sci-electronics/iverilog/files/iverilog-0.9.1-gcc45.patch b/sci-electronics/iverilog/files/iverilog-0.9.1-gcc45.patch new file mode 100644 index 000000000000..4a6914291a18 --- /dev/null +++ b/sci-electronics/iverilog/files/iverilog-0.9.1-gcc45.patch @@ -0,0 +1,37 @@ +Fixing build with gcc 4.5 + +https://bugs.gentoo.org/show_bug.cgi?id=319361 + +--- pform_disciplines.cc ++++ pform_disciplines.cc +@@ -27,8 +27,8 @@ + map disciplines; + map access_function_nature; + +-static perm_string nature_name = perm_string::perm_string(); +-static perm_string nature_access = perm_string::perm_string(); ++static perm_string nature_name = perm_string(); ++static perm_string nature_access = perm_string(); + + void pform_start_nature(const char*name) + { +@@ -82,8 +82,8 @@ + // expressions that use the access function can find it. + access_function_nature[nature_access] = tmp; + +- nature_name = perm_string::perm_string(); +- nature_access = perm_string::perm_string(); ++ nature_name = perm_string(); ++ nature_access = perm_string(); + } + + +@@ -171,7 +171,7 @@ + FILE_NAME(tmp, loc); + + /* Clear the static variables for the next item. */ +- discipline_name = perm_string::perm_string(); ++ discipline_name = perm_string(); + discipline_domain = IVL_DIS_NONE; + discipline_potential = 0; + discipline_flow = 0; diff --git a/sci-electronics/iverilog/iverilog-0.9.6.ebuild b/sci-electronics/iverilog/iverilog-0.9.6.ebuild new file mode 100644 index 000000000000..30fa882461ab --- /dev/null +++ b/sci-electronics/iverilog/iverilog-0.9.6.ebuild @@ -0,0 +1,50 @@ +# Copyright 1999-2014 Gentoo Foundation +# Distributed under the terms of the GNU General Public License v2 +# $Id$ + +EAPI=4 + +inherit eutils multilib + +DESCRIPTION="A Verilog simulation and synthesis tool" +SRC_URI="ftp://icarus.com/pub/eda/verilog/v${PV:0:3}/verilog-${PV}.tar.gz" +HOMEPAGE="http://iverilog.icarus.com/" + +LICENSE="GPL-2" +SLOT="0" +KEYWORDS="amd64 ppc sparc x86" +IUSE="examples" + +RDEPEND="app-arch/bzip2 + sys-libs/readline + sys-libs/zlib" +DEPEND="${RDEPEND}" + +S="${WORKDIR}/verilog-${PV}" + +src_prepare() { + # Fix tests + mkdir -p lib/ivl + touch lib/ivl/ivl + sed -i -e 's/driver\/iverilog -B./IVERILOG_ROOT="." driver\/iverilog -B./' Makefile.in || die + + # Fix LDFLAGS + sed -i -e 's/@shared@/@shared@ $(LDFLAGS)/' {cadpli,tgt-vhdl,tgt-null,tgt-stub,tgt-vvp}/Makefile.in || die +} + +src_install() { + emake -j1 \ + prefix="${ED}"/usr \ + mandir="${ED}"/usr/share/man \ + infodir="${ED}"/usr/share/info \ + libdir="${ED}"/usr/$(get_libdir) \ + libdir64="${ED}"/usr/$(get_libdir) \ + vpidir="${ED}"/usr/$(get_libdir)/ivl \ + install + + dodoc *.txt + if use examples ; then + insinto /usr/share/doc/${PF} + doins -r examples + fi +} diff --git a/sci-electronics/iverilog/iverilog-0.9.7.ebuild b/sci-electronics/iverilog/iverilog-0.9.7.ebuild new file mode 100644 index 000000000000..c030f5dfc0b1 --- /dev/null +++ b/sci-electronics/iverilog/iverilog-0.9.7.ebuild @@ -0,0 +1,50 @@ +# Copyright 1999-2014 Gentoo Foundation +# Distributed under the terms of the GNU General Public License v2 +# $Id$ + +EAPI=4 + +inherit eutils multilib + +DESCRIPTION="A Verilog simulation and synthesis tool" +SRC_URI="ftp://icarus.com/pub/eda/verilog/v${PV:0:3}/verilog-${PV}.tar.gz" +HOMEPAGE="http://iverilog.icarus.com/" + +LICENSE="GPL-2" +SLOT="0" +KEYWORDS="~amd64 ~ppc ~sparc ~x86" +IUSE="examples" + +RDEPEND="app-arch/bzip2 + sys-libs/readline + sys-libs/zlib" +DEPEND="${RDEPEND}" + +S="${WORKDIR}/verilog-${PV}" + +src_prepare() { + # Fix tests + mkdir -p lib/ivl + touch lib/ivl/ivl + sed -i -e 's/driver\/iverilog -B./IVERILOG_ROOT="." driver\/iverilog -B./' Makefile.in || die + + # Fix LDFLAGS + sed -i -e 's/@shared@/@shared@ $(LDFLAGS)/' {cadpli,tgt-vhdl,tgt-null,tgt-stub,tgt-vvp}/Makefile.in || die +} + +src_install() { + emake -j1 \ + prefix="${ED}"/usr \ + mandir="${ED}"/usr/share/man \ + infodir="${ED}"/usr/share/info \ + libdir="${ED}"/usr/$(get_libdir) \ + libdir64="${ED}"/usr/$(get_libdir) \ + vpidir="${ED}"/usr/$(get_libdir)/ivl \ + install + + dodoc *.txt + if use examples ; then + insinto /usr/share/doc/${PF} + doins -r examples + fi +} diff --git a/sci-electronics/iverilog/metadata.xml b/sci-electronics/iverilog/metadata.xml new file mode 100644 index 000000000000..ceafe325f3ef --- /dev/null +++ b/sci-electronics/iverilog/metadata.xml @@ -0,0 +1,11 @@ + + + + sci-electronics + + Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a + compiler, compiling source code writen in Verilog (IEEE-1364) into some target + format. The compiler proper is intended to parse and elaborate design + descriptions written to the IEEE standard IEEE Std 1364-2001. + + -- cgit v1.2.3-65-gdbad