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authorMichał Górny <mgorny@gentoo.org>2019-10-01 14:11:11 +0200
committerMichał Górny <mgorny@gentoo.org>2019-10-01 14:22:27 +0200
commit451eaa396936654d9772705c46a620bcd202fe6b (patch)
treea693c7d123063edc0979b475b0ead8f3a20497d6 /profiles/desc/llvm_targets.desc
parentprofiles/desc/llvm_targets.desc: Remove Nios2 (diff)
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profiles/desc/llvm_targets.desc: RISCV & WASM are no longer exp
Signed-off-by: Michał Górny <mgorny@gentoo.org>
Diffstat (limited to 'profiles/desc/llvm_targets.desc')
-rw-r--r--profiles/desc/llvm_targets.desc4
1 files changed, 2 insertions, 2 deletions
diff --git a/profiles/desc/llvm_targets.desc b/profiles/desc/llvm_targets.desc
index e83d886dedb9..6a45455f4c38 100644
--- a/profiles/desc/llvm_targets.desc
+++ b/profiles/desc/llvm_targets.desc
@@ -12,9 +12,9 @@ Mips - MIPS CPU target (includes MIPS64)
MSP430 - MSP430 CPU target (experimental)
NVPTX - NVIDIA PTX (GPU) target (32-bit and 64-bit)
PowerPC - PowerPC CPU target (PPC32 and PPC64)
-RISCV - RISC-V CPU target [EXPERIMENTAL]
+RISCV - RISC-V CPU target
Sparc - Sparc CPU target
SystemZ - SystemZ (s390x) CPU target
-WebAssembly - WebAssembly backend [EXPERIMENTAL]
+WebAssembly - WebAssembly backend
X86 - X86 CPU target (includes amd64)
XCore - XCore CPU target