From 451eaa396936654d9772705c46a620bcd202fe6b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20G=C3=B3rny?= Date: Tue, 1 Oct 2019 14:11:11 +0200 Subject: profiles/desc/llvm_targets.desc: RISCV & WASM are no longer exp MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michał Górny --- profiles/desc/llvm_targets.desc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'profiles/desc/llvm_targets.desc') diff --git a/profiles/desc/llvm_targets.desc b/profiles/desc/llvm_targets.desc index e83d886dedb9..6a45455f4c38 100644 --- a/profiles/desc/llvm_targets.desc +++ b/profiles/desc/llvm_targets.desc @@ -12,9 +12,9 @@ Mips - MIPS CPU target (includes MIPS64) MSP430 - MSP430 CPU target (experimental) NVPTX - NVIDIA PTX (GPU) target (32-bit and 64-bit) PowerPC - PowerPC CPU target (PPC32 and PPC64) -RISCV - RISC-V CPU target [EXPERIMENTAL] +RISCV - RISC-V CPU target Sparc - Sparc CPU target SystemZ - SystemZ (s390x) CPU target -WebAssembly - WebAssembly backend [EXPERIMENTAL] +WebAssembly - WebAssembly backend X86 - X86 CPU target (includes amd64) XCore - XCore CPU target -- cgit v1.2.3