sci-electronics/iverilog: fix compile error

Closes: https://bugs.gentoo.org/734760
Package-Manager: Portage-3.0.5, Repoman-3.0.1
Signed-off-by: Felix Neumärker <xdch47@posteo.de>
Signed-off-by: Sam James <sam@gentoo.org>

2 files changed, 173 insertions, 0 deletions

diff --git a/sci-electronics/iverilog/files/iverilog-10.3-gen-bison-header.patch b/sci-electronics/iverilog/files/iverilog-10.3-gen-bison-header.patch
new file mode 100644
index 000000000000..0027184c8338
--- /dev/null
+++ b/sci-electronics/iverilog/files/iverilog-10.3-gen-bison-header.patch
@@ -0,0 +1,97 @@
+From 5b699c1be73e789831db01e779a41478c0c62309 Mon Sep 17 00:00:00 2001
+From: Henner Zeller <h.zeller@acm.org>
+Date: Wed, 29 Jul 2020 15:29:08 -0700
+Subject: [PATCH] Bison includes its generated header in *.cc. Generate with
+ correct name.
+
+The current bison (3.7) generates a *.cc file that includes the header
+it generated. For parse.cc this would be parse.hh. Right now, we rename
+this header to have a common name used in other files, but this results
+in a compile error for the parse.cc file:
+
+parse.cc:462:10: fatal error: parse.hh: No such file or directory
+  462 | #include "parse.hh"
+      |          ^~~~~~~~~~
+
+Fix this by telling bison to output the header file to the correct
+filename in the first place so that we don't have to rename it.
+(using the --defines instead of -d option).
+
+This looks like a bison specific option not available in Posix yacc;
+but looks like we're requiring bison anyway.
+
+Signed-off-by: Henner Zeller <h.zeller@acm.org>
+---
+ Makefile.in         | 4 +---
+ tgt-pcb/Makefile.in | 4 +---
+ vhdlpp/Makefile.in  | 4 +---
+ vvp/Makefile.in     | 4 +---
+ 4 files changed, 4 insertions(+), 12 deletions(-)
+
+diff --git a/Makefile.in b/Makefile.in
+index 5ac5515a..cc8cac46 100644
+--- a/Makefile.in
++++ b/Makefile.in
+@@ -256,10 +256,8 @@ parse.o: parse.cc
+ 
+ # Build this in two steps to avoid parallel build issues (see pr3462585)
+ parse.cc: $(srcdir)/parse.y
+-	$(YACC) --verbose -t -p VL -d -o $@ $<
++	$(YACC) --verbose -t -p VL --defines=parse.h -o $@ $<
+ parse.h: parse.cc
+-	mv parse.cc.h $@ 2>/dev/null || mv parse.hh $@
+-	touch $@
+ 
+ syn-rules.cc: $(srcdir)/syn-rules.y
+ 	$(YACC) --verbose -t -p syn_ -o $@ $<
+diff --git a/tgt-pcb/Makefile.in b/tgt-pcb/Makefile.in
+index a5f9b7d5..7345e195 100644
+--- a/tgt-pcb/Makefile.in
++++ b/tgt-pcb/Makefile.in
+@@ -89,10 +89,8 @@ fp_lex.cc: $(srcdir)/fp.lex
+ 	$(LEX) -s -ofp_lex.cc $(srcdir)/fp.lex
+ 
+ fp.cc: $(srcdir)/fp.y
+-	$(YACC) --verbose -t -p fp -d -o $@ $<
++	$(YACC) --verbose -t -p fp --defines=fp.h -o $@ $<
+ fp.h: fp.cc
+-	mv fp.cc.h $@ 2>/dev/null || mv fp.hh $@
+-	touch $@
+ 
+ ifeq (@WIN32@,yes)
+   TGTLDFLAGS=-L.. -livl
+diff --git a/vhdlpp/Makefile.in b/vhdlpp/Makefile.in
+index 53ae140a..458178bd 100644
+--- a/vhdlpp/Makefile.in
++++ b/vhdlpp/Makefile.in
+@@ -117,10 +117,8 @@ lexor.cc: $(srcdir)/lexor.lex
+ 
+ # Build this in two steps to avoid parallel build issues (see pr3462585)
+ parse.cc: $(srcdir)/parse.y
+-	$(YACC) --verbose -t -d -o $@ $<
++	$(YACC) --verbose -t --defines=parse.h -o $@ $<
+ parse.h: parse.cc
+-	mv parse.cc.h $@ 2>/dev/null || mv parse.hh $@
+-	touch $@
+ 
+ lexor_keyword.o: lexor_keyword.cc parse.h
+ 
+diff --git a/vvp/Makefile.in b/vvp/Makefile.in
+index 8ccdb1d2..cdd940f5 100644
+--- a/vvp/Makefile.in
++++ b/vvp/Makefile.in
+@@ -142,10 +142,8 @@ tables.o: tables.cc
+ 
+ # Build this in two steps to avoid parallel build issues (see pr3462585)
+ parse.cc: $(srcdir)/parse.y
+-	$(YACC) --verbose -t -d -o $@ $<
++	$(YACC) --verbose -t --defines=parse.h -o $@ $<
+ parse.h: parse.cc
+-	mv parse.cc.h $@ 2>/dev/null || mv parse.hh $@
+-	touch $@
+ 
+ lexor.cc: $(srcdir)/lexor.lex
+ 	$(LEX) -s -olexor.cc $(srcdir)/lexor.lex
+-- 
+2.26.2
+
diff --git a/sci-electronics/iverilog/iverilog-10.3-r2.ebuild b/sci-electronics/iverilog/iverilog-10.3-r2.ebuild
new file mode 100644
index 000000000000..dcce51a45029
--- /dev/null
+++ b/sci-electronics/iverilog/iverilog-10.3-r2.ebuild
@@ -0,0 +1,76 @@
+# Copyright 1999-2020 Gentoo Authors
+# Distributed under the terms of the GNU General Public License v2
+
+EAPI=7
+
+inherit autotools
+
+GITHUB_PV=$(ver_rs 1- '_')
+
+DESCRIPTION="A Verilog simulation and synthesis tool"
+HOMEPAGE="
+	http://iverilog.icarus.com
+	https://github.com/steveicarus/iverilog
+"
+
+if [[ ${PV} == "9999" ]] ; then
+	inherit git-r3
+	EGIT_REPO_URI="https://github.com/steveicarus/${PN}.git"
+else
+	SRC_URI="https://github.com/steveicarus/${PN}/archive/v${GITHUB_PV}.tar.gz -> ${P}.tar.gz"
+	KEYWORDS="~alpha ~amd64 ~arm ~arm64 ~hppa ~ia64 ~m68k ~mips ~ppc ~ppc64 ~riscv ~s390 ~sparc ~x86"
+	S="${WORKDIR}/${PN}-${GITHUB_PV}"
+fi
+
+LICENSE="LGPL-2.1"
+SLOT="0"
+IUSE="examples"
+
+# If you are building from git, you will also need gperf to generate
+# the configure scripts.
+RDEPEND="
+	sys-libs/readline:=
+	sys-libs/zlib
+"
+
+DEPEND="
+	dev-util/gperf
+	sys-devel/bison
+	sys-devel/flex
+	${RDEPEND}
+"
+
+PATCHES=(
+	"${FILESDIR}"/${PN}-10.3-file-missing.patch #705412
+	"${FILESDIR}"/${PN}-10.3-fno-common.patch #706366
+	"${FILESDIR}"/${PN}-10.3-gen-bison-header.patch #734760
+)
+
+src_prepare() {
+	default
+
+	# From upstreams autoconf.sh, to make it utilize the autotools eclass
+	# Here translate the autoconf.sh, equivalent to the following code
+	# > sh autoconf.sh
+
+	# Autoconf in root ...
+	eautoconf --force
+	# Precompiling lexor_keyword.gperf
+	gperf -o -i 7 -C -k 1-4,6,9,\$ -H keyword_hash -N check_identifier -t ./lexor_keyword.gperf > lexor_keyword.cc || die
+	# Precompiling vhdlpp/lexor_keyword.gperf
+	cd vhdlpp || die
+	gperf -o -i 7 --ignore-case -C -k 1-4,6,9,\$ -H keyword_hash -N check_identifier -t ./lexor_keyword.gperf > lexor_keyword.cc || die
+}
+
+src_install() {
+	local DOCS=( *.txt )
+	# Default build fails with parallel jobs,
+	# https://github.com/steveicarus/iverilog/pull/294
+	emake installdirs DESTDIR="${D}"
+	default
+
+	if use examples; then
+		dodoc -r examples
+		docompress -x /usr/share/doc/${PF}/examples
+	fi
+}