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authorAndreas K. Hüttel <dilfridge@gentoo.org>2020-09-11 19:11:07 +0300
committerAndreas K. Hüttel <dilfridge@gentoo.org>2020-09-11 19:11:56 +0300
commit02a798126514839d6c6a1b86401a7bb35243bde2 (patch)
tree771d3c640a54781c602939fa2a81bb8c7bba373d /sys-devel
parentdev-qt/qtnetwork: add LibreSSL logic back (diff)
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sys-devel/gcc: Enable rv32 for new enough glibc
Package-Manager: Portage-3.0.4, Repoman-2.3.23 Signed-off-by: Andreas K. Hüttel <dilfridge@gentoo.org>
Diffstat (limited to 'sys-devel')
-rw-r--r--sys-devel/gcc/gcc-10.2.0-r1.ebuild5
-rw-r--r--sys-devel/gcc/gcc-10.2.1_pre9999.ebuild2
-rw-r--r--sys-devel/gcc/gcc-11.0.0_pre9999.ebuild5
3 files changed, 12 insertions, 0 deletions
diff --git a/sys-devel/gcc/gcc-10.2.0-r1.ebuild b/sys-devel/gcc/gcc-10.2.0-r1.ebuild
index 79c068077f2..2d2ebe50bce 100644
--- a/sys-devel/gcc/gcc-10.2.0-r1.ebuild
+++ b/sys-devel/gcc/gcc-10.2.0-r1.ebuild
@@ -11,3 +11,8 @@ KEYWORDS="~alpha ~amd64 ~arm ~arm64 ~hppa ~ia64 ~m68k ~mips ~ppc ~ppc64 ~riscv ~
RDEPEND=""
BDEPEND="${CATEGORY}/binutils"
+
+src_prepare() {
+ has_version '>=sys-libs/glibc-2.32-r1' && rm -v "${WORKDIR}/patch/23_all_disable-riscv32-ABIs.patch"
+ toolchain_src_prepare
+}
diff --git a/sys-devel/gcc/gcc-10.2.1_pre9999.ebuild b/sys-devel/gcc/gcc-10.2.1_pre9999.ebuild
index 5a5beeba49e..c185e457003 100644
--- a/sys-devel/gcc/gcc-10.2.1_pre9999.ebuild
+++ b/sys-devel/gcc/gcc-10.2.1_pre9999.ebuild
@@ -26,5 +26,7 @@ src_prepare() {
rm -v "${WORKDIR}/patch/$p" || die
done
+ has_version '>=sys-libs/glibc-2.32-r1' && rm -v "${WORKDIR}/patch/23_all_disable-riscv32-ABIs.patch"
+
toolchain_src_prepare
}
diff --git a/sys-devel/gcc/gcc-11.0.0_pre9999.ebuild b/sys-devel/gcc/gcc-11.0.0_pre9999.ebuild
index d3af1f28e50..db0a49eef12 100644
--- a/sys-devel/gcc/gcc-11.0.0_pre9999.ebuild
+++ b/sys-devel/gcc/gcc-11.0.0_pre9999.ebuild
@@ -15,3 +15,8 @@ EGIT_BRANCH=master
RDEPEND=""
BDEPEND="${CATEGORY}/binutils"
+
+src_prepare() {
+ has_version '>=sys-libs/glibc-2.32-r1' && rm -v "${WORKDIR}/patch/23_all_disable-riscv32-ABIs.patch"
+ toolchain_src_prepare
+}