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| author |   Sv. Lockal <lockalsash@gmail.com> | 2024-01-21 17:39:41 +0000 |
|---|---|---|
| committer |   Michał Górny <mgorny@gentoo.org> | 2024-01-22 15:08:00 +0100 |
| commit | 21e744543289f63ecba8b7df82fc3a34eb9fab79 (patch) | |
| tree | 2a4cc2231dc0f58469c1462da4e11dbba094f005 /profiles/desc/cpu_flags_x86.desc | |
| parent | dev-python/virtualenvwrapper: add missing pip test dependency (diff) | |
| download | gentoo-21e744543289f63ecba8b7df82fc3a34eb9fab79.tar.gz gentoo-21e744543289f63ecba8b7df82fc3a34eb9fab79.tar.bz2 gentoo-21e744543289f63ecba8b7df82fc3a34eb9fab79.zip | |
profiles/desc: add descriptions of vpclmulqdq and new avx512 flags
Adds description from https://github.com/projg2/cpuid2cpuflags/pull/25
Bug: https://bugs.gentoo.org/908556
Signed-off-by: Sv. Lockal <lockalsash@gmail.com>
Closes: https://github.com/gentoo/gentoo/pull/34943
Signed-off-by: Michał Górny <mgorny@gentoo.org>
Diffstat (limited to 'profiles/desc/cpu_flags_x86.desc')
| -rw-r--r-- | profiles/desc/cpu_flags_x86.desc | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/profiles/desc/cpu_flags_x86.desc b/profiles/desc/cpu_flags_x86.desc index 5c8a9bceaee6..d7dee6227a71 100644 --- a/profiles/desc/cpu_flags_x86.desc +++ b/profiles/desc/cpu_flags_x86.desc @@ -1,4 +1,4 @@ -# Copyright 1999-2019 Gentoo Authors +# Copyright 1999-2024 Gentoo Authors # Distributed under the terms of the GNU General Public License v2 # Whenever the flag name does not correspond to /proc/cpuinfo flags, @@ -10,8 +10,18 @@ aes - Enable support for Intel's AES instruction set (AES-NI) avx - Adds support for Advanced Vector Extensions instructions avx2 - Adds support for Advanced Vector Extensions 2 instructions +avx512_4fmaps - Use AVX-512 Fused Multiply-Accumulate Packed Single Precision instruction set +avx512_4vnniw - Use AVX-512 Vector Neural Network Instructions Word Variable Precision +avx512_bf16 - Use AVX-512 BFloat16 instruction set +avx512_bitalg - Use AVX-512 Bit Algorithms instruction set +avx512_fp16 - Use general-purpose numeric operations for 16-bit half-precision instruction set +avx512_vbmi2 - Use AVX-512 Vector Bit Manipulation Instructions 2 +avx512_vnni - Use vector neural network instructions for 8- and 16-bit multiply-add operations +avx512_vp2intersect - Use AVX-512 Intersect instruction set +avx512_vpopcntdq - Use AVX-512 Vector Population Count Doubleword and Quadword instruction set avx512dq - Use AVX-512 double- and quad-word instructions avx512f - Adds support for AVX-512 Foundation instructions +avx512ifma - Use AVX-512 Integer Fused Multiply-Add instruction set avx512vl - Use AVX-512 vector-length instructions f16c - Adds support for F16C instruction set for converting between half-precision and single-precision floats fma3 - Use the Fused Multiply Add 3 instruction set ([fma] in cpuinfo) @@ -30,4 +40,5 @@ sse4_1 - Enable SSE4.1 instruction support sse4_2 - Enable SSE4.2 instruction support sse4a - Enable SSE4a instruction support ssse3 - Use the SSSE3 instruction set (NOT sse3/pni) +vpclmulqdq - Use Vector Carry-Less Multiplication of Quadwords instruction set xop - Enable the XOP instruction set |